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INTEGRATED CIRCUITS
DATA SHEET
TDA8351AQ DC-coupled vertical deflection output circuit
Product specification Supersedes data of January 1995 File under Integrated Circuits, IC02 1999 Sep 27
Philips Semiconductors
Product specification
DC-coupled vertical deflection output circuit
FEATURES * Few external components * Highly efficient fully DC-coupled vertical output bridge circuit * Vertical flyback switch * Guard circuit * Protection against: - short-circuit of the output pins (9 and 5) - short-circuit of the output pins to VP * Temperature protection * High EMC immunity because of common mode inputs * A guard signal in zoom mode. QUICK REFERENCE DATA SYMBOL DC supply VP Iq Vertical circuit IO(p-p) Idiff(p-p) Vdiff(p-p) Flyback switch IM VFB peak output current flyback supply voltage note 1 Thermal data (in accordance with IEC 747-1) Tstg Tamb Tvj Note storage temperature operating ambient temperature virtual junction -55 -25 - - - - t 1.5 ms - - - - - - output current (peak-to-peak value) differential input current (peak-to-peak value) differential input voltage (peak-to-peak value) - - - - 600 1.8 supply voltage quiescent supply current 9 - 16 30 PARAMETER CONDITIONS MIN. TYP. GENERAL DESCRIPTION
TDA8351AQ
The TDA8351A is a power circuit for use in 90 and 110 colour deflection systems for field frequencies of 50 to 120 Hz. The circuit provides a DC driven vertical deflection output circuit, operating as a highly efficient class G system.
MAX.
UNIT
25 - 3 - -
V mA
A A V
1.5 50 60
A V V C C C
+150 +75 150
1. A flyback supply voltage of >50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a 22 resistor (depending on IO and the inductance of the coil) has to be connected between pin 9 and ground. The decoupling capacitor of VFB has to be connected between pin 8 and pin 4. This supply voltage line must have a resistance of 33 (see application circuit Fig.5).
1999 Sep 27
2
Philips Semiconductors
Product specification
DC-coupled vertical deflection output circuit
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8351A BLOCK DIAGRAM DBS13P DESCRIPTION
TDA8351AQ
VERSION SOT141-6
plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)
handbook, full pagewidth
VP 4 VP
VO(guard)
VFB 8
10
CURRENT SOURCE
TDA8351A
VP 9 VO(A) IS IT IT 3 VP V I(fb) VO(A)
I drive(pos)
1
I drive(neg)
2 V IS
5 VO(B)
VO(B)
7 GND
MGC055
Fig.1 Block diagram.
1999 Sep 27
3
Philips Semiconductors
Product specification
DC-coupled vertical deflection output circuit
PINNING SYMBOL Idrive(pos) Idrive(neg) VI(fb) VP VO(B) n.c. GND VFB VO(A) VO(guard) n.c. n.c. n.c. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 DESCRIPTION input power-stage (positive); includes II(sb) signal bias input power-stage (negative); includes II(sb) signal bias input feedback voltage supply voltage output voltage B not connected ground input flyback supply voltage output voltage A guard output voltage not connected not connected not connected FUNCTIONAL DESCRIPTION
TDA8351AQ
The vertical driver circuit is a bridge configuration. The deflection coil is connected between the output amplifiers, which are driven in opposite phase. An external resistor (RM) connected in series with the deflection coil provides internal feedback information. The differential input circuit is voltage driven. The input circuit has been adapted to enable it to be used with the TDA9150, TDA9151B, TDA9160A, TDA9162, TDA8366 and TDA8367 which deliver symmetrical current signals. An external resistor (RCON) connected between the differential input determines the output current through the deflection coil. The relationship between the differential input current and the output current is defined by: Idiff x RCON = Icoil x RM. The output current is adjustable from 0.5 A (p-p) to 3 A (p-p) by varying RM. The maximum input differential voltage is 1.8 V. In the application it is recommended that Vdiff = 1.5 V (typ). This is recommended because of the spread of input current and the spread in the value of RCON. The flyback voltage is determined by an additional supply voltage VFB. The principle of operating with two supply voltages (class G) makes it possible to fix the supply voltage VP optimum for the scan voltage and the second supply voltage VFB optimum for the flyback voltage. Using this method, very high efficiency is achieved. The supply voltage VFB is almost totally available as flyback voltage across the coil, this being possible due to the absence of a decoupling capacitor (not necessary, due to the bridge configuration). Built-in protections are: * thermal protection * short-circuit protection of the output pins (pins 5 and 9) * short-circuit protection of the output pins to VP. A guard circuit VO(guard) is provided. The guard circuit is activated at the following conditions: * during flyback * during short-circuit of the coil and during short-circuit of the output pins (pins 5 and 9) to VP or ground * during open loop * when the thermal protection is activated. This signal can be used for blanking the picture tube screen.
handbook, halfpage
I drive(pos) I drive(neg) V I(fb) Vp VO(B) n.c. GND V FB VO(A)
1 2 3 4 5 6 7 8 9
TDA8351A
VO(guard) 10 n.c. 11 n.c. 12 n.c. 13
MGC056
The die has been glued to the metal block of the package. If the metal block is not insulated from the heat sink, the heat sink may only be connected directly to pin 7.
Fig.2 Pin configuration.
1999 Sep 27
4
Philips Semiconductors
Product specification
DC-coupled vertical deflection output circuit
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL DC supply VP VFB Vertical circuit IO(p-p) VO(A) Flyback switch IM Tstg Tamb Tvj Rth vj-c Rth vj-a tsc Notes peak output current - -55 -25 - - - note 3 - output current (peak-to-peak value) output voltage (pin 7) note 1 note 2 - - - supply voltage flyback supply voltage note 1 non-operating - - - - PARAMETER CONDITIONS MIN.
TDA8351AQ
MAX.
UNIT
40 25 50 60
V V V V
3 52 62 1.5 +150 +75 150 4 40 1
A V V
A C C C K/W K/W hr
Thermal data (in accordance with IEC 747-1) storage temperature operating ambient temperature virtual junction temperature resistance vj-case resistance vj-ambient in free air short-circuiting time
1. A flyback supply voltage of >50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a 22 resistor (depending on IO and the inductance of the coil) has to be connected between pin 9 and ground. The decoupling capacitor of VFB has to be connected between pin 8 and pin 4. This supply voltage line must have a resistance of 33 (see application circuit Fig.5). 2. IO maximum determined by current protection. 3. Up to VP = 18 V.
1999 Sep 27
5
Philips Semiconductors
Product specification
DC-coupled vertical deflection output circuit
TDA8351AQ
CHARACTERISTICS VP = 17.5 V; VFB = 45 V; fi = 50 Hz; II(sb) = 400 A; Tamb = 25 C; measured in test circuit of Fig.3; unless otherwise specified. SYMBOL DC supply VP VFB IP VO operating supply voltage flyback supply voltage note 1 supply current no signal; no load Vertical circuit output voltage swing (scan) Idiff = 0.6 mA (p-p); Vdiff = 1.8 V (p-p); IO = 3 A (p-p) IO = 3 A (p-p); note 2 IO = 50 mA (p-p); note 2 VO VDF |Ios| |Vos| VosT VO(A) Gvo output voltage swing (flyback) VO(A) - VO(B) forward voltage of the internal efficiency diode (VO(A) - VFB) output offset current offset voltage at the input of the feedback amplifier (VI(fb) - VO(B)) Idiff = 0.3 mA; IO = 1.5 A IO = -1.5 A; Idiff = 0.3 mA Idiff = 0; II(sb) = 50 to 500 A Idiff = 0; II(sb) = 50 to 500 A 19.8 - - V 9.0 VP VP - - - - 30 25 50 60 55 V V V mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
LE
linearity error
- - - - - - - - - - -
1 1 39 - - - - 8.0 80 80 0 40 5000 - 400 - 80 2.7 - 0.1 0.2
3 3 - 1.5 30 18 72 - - - - - - 10-4 500 100 - - 1.6 0.5 -
% % V V mA mV V/K V dB dB dB Hz K A A dB V V A mA
output offset voltage as a function Idiff = 0 of temperature DC output voltage open loop voltage gain (V9-5/V3-5; V1-2 = 0) Idiff = 0; note 3 note 4 open-loop voltage gain (V9-5/V1-2) notes 4 and 5
VR fres GI GcT II(sb) IFB PSRR VI(DC) VI(CM) Ibias IO(CM)
voltage ratio V1-2/V3-5 frequency response (-3 dB) current gain (IO/Idiff) current gain drift as a function of temperature signal bias current flyback supply current power supply ripple rejection DC input voltage common mode input voltage input bias current common mode output current II(sb) = 0 II(sb) = 0 II(sb) = 300 A (p-p); fi = 50 Hz; Idiff = 0 during scan note 7 open loop; note 6
- - - 50 - - - 0 - -
1999 Sep 27
6
Philips Semiconductors
Product specification
DC-coupled vertical deflection output circuit
SYMBOL Guard circuit IO output current not active; VO(guard) = 0 V active; VO(guard) = 3.6 V VO(guard) output voltage on pin 8 allowable voltage on pin 8 Notes IO = 100 A maximum leakage current = 10 A; - 1 4.6 - - - - - PARAMETER CONDITIONS MIN. TYP.
TDA8351AQ
MAX.
UNIT A mA V V
50 2.5 5.5 40
1. A flyback supply voltage of >50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a 22 resistor (depending on IO and the inductance of the coil) has to be connected between pin 9 and ground. The decoupling capacitor of VFB has to be connected between pin 8 and pin 4. This supply voltage line must have a resistance of 33 (see application circuit Fig.5). 2. The linearity error is measured without S-correction and based on the same measurement principle as performed on the screen. The measuring method is as follows: Divide the output signal I5 - I9 (VRM) into 22 equal parts ranging from 1 to 22 inclusive. Measure the value of two succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part 20 and 21 (block 10). Thus part 1 and 22 are unused. The equations for linearity error for adjacent blocks (LEAB) and linearity error for not adjacent blocks (LENAB) are given below: a max - a min ak - a( k + 1 LEAB = ---------------------------) ; LENAB = ----------------------------a avg a avg 3. Referenced to VP. 4. The V values within formulae relate to voltages at or across relative pin numbers, i.e. V9-5/V1-2 = voltage value across pins 9 and 5 divided by voltage value across pins 1 and 2. 5. V9-4 AC short-circuited. 6. Frequency response V9-5/V3-5 is equal to frequency response V9-5/V1-2. 7. At V(ripple) = 500 mV eff; measured across RM; fi = 50 Hz.
1999 Sep 27
7
Philips Semiconductors
Product specification
DC-coupled vertical deflection output circuit
TDA8351AQ
handbook, full pagewidth
2.2 k VO(guard) 10 I I(sb) signal bias I drive(pos) R CON 3 k I drive(neg) signal bias I I(sb) I diff 2 V 5 1 FEEDBACK 3 INPUT 8 4 VP
VFB
TDA8351A
9 R = 6.0
R M = 0.7
7 GND
MGC057
Fig.3 Test diagram.
1999 Sep 27
8
Philips Semiconductors
Product specification
DC-coupled vertical deflection output circuit
APPLICATION INFORMATION
TDA8351AQ
handbook, full pagewidth
VO(guard) 10 II(sb) signal bias Idrive(pos) RCON 3 k Idrive(neg) signal bias II(sb) Idiff 2 V 1 FEEDBACK 3 INPUT 8 4
VFB 100 nF 10 nF 10 F VP 100 nF 9 VO(A) I(coil) deflection coil AT6005/31 L = 8.63 mH R = 5.0 RM = 0.7 100 F
TDA8351A
VI(fB)
5 VO(B)
7 GND
MGL860
VP = 14 V; IO(p-p) = 2.14 A; II(sb) = 400 A; Idiff(p-p) = 500 A; VFB = 42 V; tFB = 0.6 ms.
Fig.4 Application diagram.
1999 Sep 27
9
Philips Semiconductors
Product specification
DC-coupled vertical deflection output circuit
TDA8351AQ
handbook, full pagewidth
30 VO(guard) 10 8 4 100 nF 9 VO(A) 1 RCON 3 k Idiff 2 V I(coil) V FEEDBACK 3 I(fB) INPUT RM = 0.7 5 VO(B) 470 nF 20 deflection coil AT6005/31 L = 8.63 mH R = 5.0 100 F VFB 100 nF 10 nF 10 F VP
II(sb) signal bias Idrive(pos)
TDA8351A
Idrive(neg) signal bias II(sb)
7 GND
MGC861
VP = 14 V; IO(p-p) = 2.14 A; II(sb) = 400 A; Idiff(p-p) = 500 A; VFB = 60 V; tFB = 0.4 ms.
Fig.5 Application circuit; 50 V VFB 60 V.
1999 Sep 27
10
Philips Semiconductors
Product specification
DC-coupled vertical deflection output circuit
PACKAGE OUTLINE DBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)
TDA8351AQ
SOT141-6
non-concave x D Dh
Eh
view B: mounting base side
d
A2
B j E A
L3
L
Q c vM
1 Z e e1 bp wM
13 m e2
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT141-6 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A 17.0 15.5 A2 4.6 4.2 bp 0.75 0.60 c 0.48 0.38 D (1) 24.0 23.6 d 20.0 19.6 Dh 10 E (1) 12.2 11.8 e 3.4 e1 1.7 e2 5.08 Eh 6 j 3.4 3.1 L 12.4 11.0 L3 2.4 1.6 m 4.3 Q 2.1 1.8 v 0.8 w 0.25 x 0.03 Z (1) 2.00 1.45
ISSUE DATE 95-03-11 97-12-16
1999 Sep 27
11
Philips Semiconductors
Product specification
DC-coupled vertical deflection output circuit
SOLDERING Introduction to soldering through-hole mount packages This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds.
TDA8351AQ
The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. suitable suitable(1) WAVE
1999 Sep 27
12
Philips Semiconductors
Product specification
DC-coupled vertical deflection output circuit
NOTES
TDA8351AQ
1999 Sep 27
13
Philips Semiconductors
Product specification
DC-coupled vertical deflection output circuit
NOTES
TDA8351AQ
1999 Sep 27
14
Philips Semiconductors
Product specification
DC-coupled vertical deflection output circuit
NOTES
TDA8351AQ
1999 Sep 27
15
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 68
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/02/pp16
Date of release: 1999
Sep 27
Document order number:
9397 750 06204

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